Programming and Verifying Real-Time Design Using Logical Time

Abstract

This work investigates the relationship between Synchronous-Reactive languages, Logical Execution Time, and the industrial PsyC language. It outlines how synchronous representations can provide a route toward functional and logical-time verification techniques for PsyC programs.

Publication
Forum on Specification & Design Languages (FDL 2021), PhD/WiP Forum
Fabien Siron
Fabien Siron
Research Engineer | Lecturer

Research engineer working on formal verification, synchronous-reactive systems and safety-critical real-time software.